BEGIN:VCALENDAR VERSION:2.0 PRODID:-//CAD MicroSolutions Inc. - ECPv6.15.15//NONSGML v1.0//EN CALSCALE:GREGORIAN METHOD:PUBLISH X-ORIGINAL-URL:https://www.cadmicro.com X-WR-CALDESC:Events for CAD MicroSolutions Inc. REFRESH-INTERVAL;VALUE=DURATION:PT1H X-Robots-Tag:noindex X-PUBLISHED-TTL:PT1H BEGIN:VTIMEZONE TZID:America/Toronto BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20240310T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20241103T060000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20250309T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20251102T060000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20260308T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20261101T060000 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250623T130000 DTEND;TZID=America/Toronto:20250626T160000 DTSTAMP:20260422T033910 CREATED:20240209T152932Z LAST-MODIFIED:20250313T173858Z UID:56296-1750683600-1750953600@www.cadmicro.com SUMMARY:SOLIDWORKS Routing: Electrical - Online DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-routing-electrical-online/ CATEGORIES:Training ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/Electrical-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250716T110000 DTEND;TZID=America/Toronto:20250716T113000 DTSTAMP:20260422T033910 CREATED:20250610T150109Z LAST-MODIFIED:20250610T150717Z UID:74788-1752663600-1752665400@www.cadmicro.com SUMMARY:How to Leverage PSpice for Pre-Layout Simulation DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/how-to-leverage-pspice-for-pre-layout-simulation/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/webp:https://www.cadmicro.com/wp-content/uploads/pspice.webp END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250729T110000 DTEND;TZID=America/Toronto:20250729T120000 DTSTAMP:20260422T033910 CREATED:20250611T140649Z LAST-MODIFIED:20250611T140958Z UID:74795-1753786800-1753790400@www.cadmicro.com SUMMARY:Life-Changing Prosthetics for Kids: A Fireside Chat on Innovation and Compassionate Care DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/life-changing-prosthetics-for-kids-a-fireside-chat-on-innovation-and-compassionate-care/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/webp:https://www.cadmicro.com/wp-content/uploads/website-HP-webinar-July-29.webp END:VEVENT END:VCALENDAR