BEGIN:VCALENDAR VERSION:2.0 PRODID:-//CAD MicroSolutions Inc. - ECPv6.15.15//NONSGML v1.0//EN CALSCALE:GREGORIAN METHOD:PUBLISH X-ORIGINAL-URL:https://www.cadmicro.com X-WR-CALDESC:Events for CAD MicroSolutions Inc. REFRESH-INTERVAL;VALUE=DURATION:PT1H X-Robots-Tag:noindex X-PUBLISHED-TTL:PT1H BEGIN:VTIMEZONE TZID:America/Toronto BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20240310T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20241103T060000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20250309T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20251102T060000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20260308T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20261101T060000 END:STANDARD END:VTIMEZONE BEGIN:VTIMEZONE TZID:America/Edmonton BEGIN:DAYLIGHT TZOFFSETFROM:-0700 TZOFFSETTO:-0600 TZNAME:MDT DTSTART:20240310T090000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0600 TZOFFSETTO:-0700 TZNAME:MST DTSTART:20241103T080000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0700 TZOFFSETTO:-0600 TZNAME:MDT DTSTART:20250309T090000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0600 TZOFFSETTO:-0700 TZNAME:MST DTSTART:20251102T080000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0700 TZOFFSETTO:-0600 TZNAME:MDT DTSTART:20260308T090000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0600 TZOFFSETTO:-0700 TZNAME:MST DTSTART:20261101T080000 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250508T130000 DTEND;TZID=America/Toronto:20250508T140000 DTSTAMP:20260422T041831 CREATED:20250430T141953Z LAST-MODIFIED:20250430T142345Z UID:73886-1746709200-1746712800@www.cadmicro.com SUMMARY:From Chaos to Clarity: AI-Driven Planning for Manufacturers in the Real World DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/from-chaos-to-clarity-ai-driven-planning-for-manufacturers-in-the-real-world/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/event_629fb36a-fa27-4ba6-8d3d-2451c4b4c1c6_resources_M8wds2AaRFOJd1MKw0jU_delmia2-1.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250512T130000 DTEND;TZID=America/Toronto:20250522T160000 DTSTAMP:20260422T041831 CREATED:20250501T185445Z LAST-MODIFIED:20250501T185549Z UID:73986-1747054800-1747929600@www.cadmicro.com SUMMARY:SOLIDWORKS Essentials - Online DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-essentials-online-6/ CATEGORIES:Training ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/SW-CAD-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250514T110000 DTEND;TZID=America/Toronto:20250514T113000 DTSTAMP:20260422T041831 CREATED:20250501T181013Z LAST-MODIFIED:20250501T182624Z UID:73972-1747220400-1747222200@www.cadmicro.com SUMMARY:Simplifying ECAD Design Sharing\, Reviews\, and Teamwork DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/simplifying-ecad-design-sharing-reviews-and-teamwork/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/webp:https://www.cadmicro.com/wp-content/uploads/orcad-x-website.webp END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250514T150000 DTEND;TZID=America/Toronto:20250514T160000 DTSTAMP:20260422T041831 CREATED:20250430T152312Z LAST-MODIFIED:20250430T152548Z UID:73949-1747234800-1747238400@www.cadmicro.com SUMMARY:Aircraft Lightning Strike Analysis Using SIMULIA CST Studio Suite DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/aircraft-lightning-strike-analysis-using-simulia-cst-studio-suite/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/event_3ddd3ab3-b3ac-4c0f-9b41-25990dfe9a2d_resources_FOXfotCSw2J58cu4ynod_cst1.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250515T130000 DTEND;TZID=America/Toronto:20250515T140000 DTSTAMP:20260422T041831 CREATED:20250430T145656Z LAST-MODIFIED:20250501T183314Z UID:73906-1747314000-1747317600@www.cadmicro.com SUMMARY:Work Smarter\, Not Harder: Data Reuse in Electrical Design DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/work-smarter-not-harder-data-reuse-in-electrical-design/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/webp:https://www.cadmicro.com/wp-content/uploads/May-15-electrical.webp END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250515T150000 DTEND;TZID=America/Toronto:20250515T153000 DTSTAMP:20260422T041831 CREATED:20250430T150021Z LAST-MODIFIED:20250430T150235Z UID:73912-1747321200-1747323000@www.cadmicro.com SUMMARY:Professional SOLIDWORKS Training Portfolio with GoEngineer DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/professional-solidworks-training-portfolio-with-goengineer/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/May-15-SW-training.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250519T090000 DTEND;TZID=America/Toronto:20250523T120000 DTSTAMP:20260422T041831 CREATED:20250313T204440Z LAST-MODIFIED:20250501T190708Z UID:72760-1747645200-1748001600@www.cadmicro.com SUMMARY:SOLIDWORKS Drawings - Online DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-drawings-online/ CATEGORIES:Training ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/SW-CAD-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250519T130000 DTEND;TZID=America/Toronto:20250522T160000 DTSTAMP:20260422T041831 CREATED:20241126T181011Z LAST-MODIFIED:20250501T190924Z UID:68757-1747659600-1747929600@www.cadmicro.com SUMMARY:SOLIDWORKS Sheet Metal Training - Online DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-sheet-metal-training-online/ CATEGORIES:Training ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/SW-CAD-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250520T090000 DTEND;TZID=America/Toronto:20250530T120000 DTSTAMP:20260422T041831 CREATED:20250501T185654Z LAST-MODIFIED:20250501T190216Z UID:73992-1747731600-1748606400@www.cadmicro.com SUMMARY:SOLIDWORKS Essentials - Online DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-essentials-online-7/ CATEGORIES:Training ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/SW-CAD-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250520T150000 DTEND;TZID=America/Toronto:20250520T160000 DTSTAMP:20260422T041831 CREATED:20250430T150726Z LAST-MODIFIED:20250430T150916Z UID:73923-1747753200-1747756800@www.cadmicro.com SUMMARY:SOLIDWORKS Vibration: From Beginning to End DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-vibration-from-beginning-to-end/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/May-20-SW-Vibration.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250520T150000 DTEND;TZID=America/Toronto:20250520T160000 DTSTAMP:20260422T041831 CREATED:20250508T200451Z LAST-MODIFIED:20250508T201312Z UID:74334-1747753200-1747756800@www.cadmicro.com SUMMARY:Unlock Aerospace Innovation with Markforged DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/unlock-aerospace-innovation-with-markforged/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/webp:https://www.cadmicro.com/wp-content/uploads/industry-aerospace-hero_2x.webp END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250521T120000 DTEND;TZID=America/Toronto:20250521T140000 DTSTAMP:20260422T041831 CREATED:20250514T133449Z LAST-MODIFIED:20250514T133745Z UID:74517-1747828800-1747836000@www.cadmicro.com SUMMARY:Virtual Hands-On Test Drive: SOLIDWORKS Simulation Professional DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/virtual-hands-on-test-drive-solidworks-simulation-professional/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/Sim-Training-Thumbnail.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250522T150000 DTEND;TZID=America/Toronto:20250522T160000 DTSTAMP:20260422T041831 CREATED:20250430T151034Z LAST-MODIFIED:20250430T151243Z UID:73933-1747926000-1747929600@www.cadmicro.com SUMMARY:Mastering SOLIDWORKS Drawings DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/mastering-solidworks-drawings/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/May-22-SW-drawings.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250527T090000 DTEND;TZID=America/Toronto:20250527T160000 DTSTAMP:20260422T041831 CREATED:20230823T174344Z LAST-MODIFIED:20250303T202407Z UID:51581-1748336400-1748361600@www.cadmicro.com SUMMARY:DEX Expo - Ottawa DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/dex-expo-ottawa/ LOCATION:Nepean Sportsplex\, Building B\, 1701 Woodroffe Ave\, Ottawa\, Ontario\, K2G1W2\, Canada CATEGORIES:Trade Show ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/DEX-Show-Website-Image-2.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250527T090000 DTEND;TZID=America/Toronto:20250530T120000 DTSTAMP:20260422T041831 CREATED:20240130T144402Z LAST-MODIFIED:20250313T173456Z UID:55746-1748336400-1748606400@www.cadmicro.com SUMMARY:SOLIDWORKS CAM Standard Training – Online DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-cam-standard-training-online-2/ CATEGORIES:Training ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/CAM-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250527T130000 DTEND;TZID=America/Toronto:20250529T160000 DTSTAMP:20260422T041831 CREATED:20250313T205103Z LAST-MODIFIED:20250512T192419Z UID:72766-1748350800-1748534400@www.cadmicro.com SUMMARY:SOLIDWORKS Weldments - Online DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-weldments-online/ CATEGORIES:Training ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/SW-CAD-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250527T130000 DTEND;TZID=America/Toronto:20250530T160000 DTSTAMP:20260422T041831 CREATED:20231213T144102Z LAST-MODIFIED:20250512T192531Z UID:54503-1748350800-1748620800@www.cadmicro.com SUMMARY:SOLIDWORKS Surface Modeling Training – Online DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-surface-modeling-training-online-3/ CATEGORIES:Training ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/SW-CAD-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250527T130000 DTEND;TZID=America/Toronto:20250606T160000 DTSTAMP:20260422T041831 CREATED:20250501T190008Z LAST-MODIFIED:20250501T190123Z UID:73997-1748350800-1749225600@www.cadmicro.com SUMMARY:SOLIDWORKS Essentials - Online DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-essentials-online-8/ CATEGORIES:Training ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/SW-CAD-Training-Thumbnail.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250528T090000 DTEND;TZID=America/Toronto:20250529T170000 DTSTAMP:20260422T041831 CREATED:20250505T193452Z LAST-MODIFIED:20250505T194759Z UID:74074-1748422800-1748538000@www.cadmicro.com SUMMARY:CANSEC 2025 DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/cansec-2025/ CATEGORIES:Trade Show ATTACH;FMTTYPE=image/webp:https://www.cadmicro.com/wp-content/uploads/CANSEC-2025.webp ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250529T110000 DTEND;TZID=America/Toronto:20250529T113000 DTSTAMP:20260422T041831 CREATED:20250509T140045Z LAST-MODIFIED:20250509T140529Z UID:74347-1748516400-1748518200@www.cadmicro.com SUMMARY:How the Jet Fusion 3D Printer Works and its Benefits DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/how-the-jet-fusion-3d-printer-works-and-its-benefits/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/webp:https://www.cadmicro.com/wp-content/uploads/HP-Polymers.webp END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250602T090000 DTEND;TZID=America/Toronto:20250606T170000 DTSTAMP:20260422T041831 CREATED:20240920T173700Z LAST-MODIFIED:20250430T160810Z UID:66238-1748854800-1749229200@www.cadmicro.com SUMMARY:SOLIDWORKS Essentials: Parts\, Assemblies & Drawings – Cambridge DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-parts-assemblies-drawings-cambridge-june/ LOCATION:CAD Micro – Cambridge\, 225 Pinebush Road\, Unit 102\, Cambridge\, Ontario\, N1T1B9\, Canada CATEGORIES:Training ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/SW-CAD-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250602T090000 DTEND;TZID=America/Toronto:20250612T120000 DTSTAMP:20260422T041831 CREATED:20231213T151816Z LAST-MODIFIED:20250512T193949Z UID:54572-1748854800-1749729600@www.cadmicro.com SUMMARY:SOLIDWORKS Essentials - Online DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-parts-assemblies-online1/ CATEGORIES:Training ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/SW-CAD-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250602T130000 DTEND;TZID=America/Toronto:20250611T160000 DTSTAMP:20260422T041831 CREATED:20241007T194231Z LAST-MODIFIED:20250512T193000Z UID:67140-1748869200-1749657600@www.cadmicro.com SUMMARY:SOLIDWORKS Electrical Schematics - Online DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-electrical-schematics-online/ CATEGORIES:Training ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/Electrical-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250602T130000 DTEND;TZID=America/Toronto:20250612T160000 DTSTAMP:20260422T041831 CREATED:20250313T151103Z LAST-MODIFIED:20250512T194335Z UID:72615-1748869200-1749744000@www.cadmicro.com SUMMARY:SOLIDWORKS Essentials - Online DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-essentials-online-2/ CATEGORIES:Training ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/SW-CAD-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250604T110000 DTEND;TZID=America/Toronto:20250604T113000 DTSTAMP:20260422T041831 CREATED:20250527T183530Z LAST-MODIFIED:20250527T193313Z UID:74657-1749034800-1749036600@www.cadmicro.com SUMMARY:Transforming RF PCB Design: Advanced Co-Simulation and EM Analysis DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/transforming-rf-pcb-design-advanced-co-simulation-and-em-analysis/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/png:https://www.cadmicro.com/wp-content/uploads/pcb-website.png END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250604T120000 DTEND;TZID=America/Toronto:20250604T160000 DTSTAMP:20260422T041831 CREATED:20240429T181047Z LAST-MODIFIED:20250512T195407Z UID:61060-1749038400-1749052800@www.cadmicro.com SUMMARY:Advanced Manufacturing Open House DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/advanced-manufacturing-open-house-6/ LOCATION:CAD Micro\, 30 International Blvd\, Unit 1\, Toronto\, Ontario\, M9W 1A2\, Canada CATEGORIES:In Person Event ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/SmartMTX-Event-Page-Image-1.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250605T090000 DTEND;TZID=America/Toronto:20250605T120000 DTSTAMP:20260422T041831 CREATED:20240429T182622Z LAST-MODIFIED:20250512T195620Z UID:61094-1749114000-1749124800@www.cadmicro.com SUMMARY:Simulation Hands-On Test Drive DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/simulation-hands-on-test-drive-6/ LOCATION:CAD Micro\, 30 International Blvd\, Unit 1\, Toronto\, Ontario\, M9W 1A2\, Canada CATEGORIES:In Person Event ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/Sim-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250605T130000 DTEND;TZID=America/Toronto:20250605T140000 DTSTAMP:20260422T041831 CREATED:20250528T200820Z LAST-MODIFIED:20250528T201035Z UID:74672-1749128400-1749132000@www.cadmicro.com SUMMARY:The SOLIDWORKS Sim-Posium: Simulation Hardware Recommendations DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/the-solidworks-sim-posium-simulation-hardware-recommendations/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/event_b818e9c1-2a23-40e9-8677-bc7a7131380c_resources_DOMWFOxpQwCRaphndgqB_The-SOLIDWORKS-Sim-Posium-Simulation-Hardware-Recommendations-2-1.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250609T130000 DTEND;TZID=America/Toronto:20250613T160000 DTSTAMP:20260422T041831 CREATED:20231213T155717Z LAST-MODIFIED:20250512T192711Z UID:54618-1749474000-1749830400@www.cadmicro.com SUMMARY:SOLIDWORKS Simulation Essentials - Online DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-simulation-essentials-online-6/ CATEGORIES:Training ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/Sim-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Edmonton:20250610T100000 DTEND;TZID=America/Edmonton:20250612T170000 DTSTAMP:20260422T041831 CREATED:20250514T134523Z LAST-MODIFIED:20250514T140252Z UID:74527-1749549600-1749747600@www.cadmicro.com SUMMARY:Global Energy Show DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/global-energy-show/ LOCATION:BMO Centre at Stampede Park\, 20 Roundup Way SE\, Calgary\, Alberta\, T2G 2W1\, Canada CATEGORIES:Trade Show ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/Global-Energy-Show-2023-1.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT END:VCALENDAR