BEGIN:VCALENDAR VERSION:2.0 PRODID:-//CAD MicroSolutions Inc. - ECPv6.15.15//NONSGML v1.0//EN CALSCALE:GREGORIAN METHOD:PUBLISH X-ORIGINAL-URL:https://www.cadmicro.com X-WR-CALDESC:Events for CAD MicroSolutions Inc. REFRESH-INTERVAL;VALUE=DURATION:PT1H X-Robots-Tag:noindex X-PUBLISHED-TTL:PT1H BEGIN:VTIMEZONE TZID:America/Toronto BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20240310T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20241103T060000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20250309T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20251102T060000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20260308T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20261101T060000 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250311T090000 DTEND;TZID=America/Toronto:20250313T170000 DTSTAMP:20260406T114600 CREATED:20241029T173410Z LAST-MODIFIED:20241029T173535Z UID:67764-1741683600-1741885200@www.cadmicro.com SUMMARY:CAMWorks Essentials 3 Axis – Online DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/camworks-essentials-3-axis-online/ CATEGORIES:Training ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/CAM-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250311T110000 DTEND;TZID=America/Toronto:20250311T120000 DTSTAMP:20260406T114600 CREATED:20240926T143713Z LAST-MODIFIED:20250303T192039Z UID:66510-1741690800-1741694400@www.cadmicro.com SUMMARY:Introduction to Using DriveWorks for Automating Your SOLIDWORKS Designs DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/introduction-to-using-driveworks-for-automating-your-solidworks-designs-3/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/DriveWorks-Automate-SW-Designs-Website.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250311T150000 DTEND;TZID=America/Toronto:20250311T160000 DTSTAMP:20260406T114600 CREATED:20250303T183803Z LAST-MODIFIED:20250303T185257Z UID:72212-1741705200-1741708800@www.cadmicro.com SUMMARY:Flow Simulation: Optimizing Huge Heat Sinks DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/flow-simulation-optimizing-huge-heat-sinks/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/webp:https://www.cadmicro.com/wp-content/uploads/event_67bfebcc-b3e7-44e0-be30-0262c8433ba0_resources_x73oIBQRRiNJM9fDgJdM_flow-simulation.webp END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250313T090000 DTEND;TZID=America/Toronto:20250313T140000 DTSTAMP:20260406T114600 CREATED:20241029T194228Z LAST-MODIFIED:20241029T194323Z UID:67849-1741856400-1741874400@www.cadmicro.com SUMMARY:Simulation Hands-On Test Drive DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/simulation-hands-on-test-drive-13/ LOCATION:CAD Micro\, 30 International Blvd\, Unit 1\, Toronto\, Ontario\, M9W 1A2\, Canada CATEGORIES:In Person Event ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/Sim-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250317T090000 DTEND;TZID=America/Toronto:20250321T170000 DTSTAMP:20260406T114600 CREATED:20241029T132104Z LAST-MODIFIED:20241029T132210Z UID:67698-1742202000-1742576400@www.cadmicro.com SUMMARY:SOLIDWORKS Essentials: Parts\, Assemblies & Drawings – Cambridge DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-essentials-parts-assemblies-drawings-cambridge/ LOCATION:CAD Micro – Cambridge\, 225 Pinebush Road\, Unit 102\, Cambridge\, Ontario\, N1T1B9\, Canada CATEGORIES:Training ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/SW-CAD-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250318T083000 DTEND;TZID=America/Toronto:20250319T123000 DTSTAMP:20260406T114600 CREATED:20241209T150946Z LAST-MODIFIED:20241210T184419Z UID:69469-1742286600-1742387400@www.cadmicro.com SUMMARY:3DEXPERIENCE Administration Essentials – Online DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/3dexperience-administration-essentials-online-2/ CATEGORIES:Training ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/3DX-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250318T110000 DTEND;TZID=America/Toronto:20250318T120000 DTSTAMP:20260406T114600 CREATED:20240926T145212Z LAST-MODIFIED:20250303T181608Z UID:66524-1742295600-1742299200@www.cadmicro.com SUMMARY:Introduction to Using DriveWorks as a 3D Sales Configurator DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/introduction-to-using-driveworks-as-a-3d-sales-configurator-3/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/DriveWorks-3D-Sales-Configurator-Website.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250319T110000 DTEND;TZID=America/Toronto:20250319T113000 DTSTAMP:20260406T114600 CREATED:20250224T202214Z LAST-MODIFIED:20250314T175235Z UID:71931-1742382000-1742383800@www.cadmicro.com SUMMARY:PCB Libraries Made Easy: Create\, Manage\, and Optimize DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/pcb-libraries-made-easy-create-manage-and-optimize/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/Cadence-PCB-webinar-1-scaled.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250319T120000 DTEND;TZID=America/Toronto:20250319T160000 DTSTAMP:20260406T114600 CREATED:20241029T194033Z LAST-MODIFIED:20241029T194130Z UID:67843-1742385600-1742400000@www.cadmicro.com SUMMARY:Additive Manufacturing Open House DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/additive-manufacturing-open-house-14/ LOCATION:CAD Micro\, 30 International Blvd\, Unit 1\, Toronto\, Ontario\, M9W 1A2\, Canada CATEGORIES:In Person Event ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/3DP-1.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250320T090000 DTEND;TZID=America/Toronto:20250320T160000 DTSTAMP:20260406T114600 CREATED:20241029T194359Z LAST-MODIFIED:20241029T194445Z UID:67855-1742461200-1742486400@www.cadmicro.com SUMMARY:Simulation Demo Day DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/simulation-demo-day-13/ LOCATION:CAD Micro\, 30 International Blvd\, Unit 1\, Toronto\, Ontario\, M9W 1A2\, Canada CATEGORIES:In Person Event ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/Adv-Sim-Summit-Website-Image.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250321T150000 DTEND;TZID=America/Toronto:20250321T160000 DTSTAMP:20260406T114600 CREATED:20250303T184848Z LAST-MODIFIED:20250303T191013Z UID:72219-1742569200-1742572800@www.cadmicro.com SUMMARY:How DriveWorks Enhances Collaboration Between Sales and Engineering DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/how-driveworks-enhances-collaboration-between-sales-and-engineering/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/webp:https://www.cadmicro.com/wp-content/uploads/event_e9b17268-8c20-437d-9345-5f46fbd8604d_resources_aBCFlKZOT6yxWvkUsrOu_Handshake.webp END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250325T090000 DTEND;TZID=America/Toronto:20250326T170000 DTSTAMP:20260406T114600 CREATED:20241029T172710Z LAST-MODIFIED:20241029T172906Z UID:67752-1742893200-1743008400@www.cadmicro.com SUMMARY:SOLIDWORKS Routing: Electrical – Online DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-routing-electrical-online-4/ CATEGORIES:Training ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/Electrical-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250325T110000 DTEND;TZID=America/Toronto:20250325T120000 DTSTAMP:20260406T114600 CREATED:20240925T172519Z LAST-MODIFIED:20250303T182444Z UID:66442-1742900400-1742904000@www.cadmicro.com SUMMARY:Introduction to Creating a CPQ Solution Using DriveWorks DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/introduction-to-creating-a-cpq-solution-using-driveworks/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/DriveWorks-CPQ-Solution-Website.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250326T090000 DTEND;TZID=America/Toronto:20250327T170000 DTSTAMP:20260406T114600 CREATED:20241126T162336Z LAST-MODIFIED:20241209T151443Z UID:68737-1742979600-1743094800@www.cadmicro.com SUMMARY:SOLIDWORKS Simulation Dynamics Training - Online DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-simulation-dynamics-training-online-5/ CATEGORIES:Training ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/Sim-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250326T110000 DTEND;TZID=America/Toronto:20250326T113000 DTSTAMP:20260406T114601 CREATED:20250314T135721Z LAST-MODIFIED:20250314T140328Z UID:72779-1742986800-1742988600@www.cadmicro.com SUMMARY:Leveraging Constraint Sets for DDRx Design in Allegro X DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/leveraging-constraint-sets-for-ddrx-design-in-allegro-x/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/png:https://www.cadmicro.com/wp-content/uploads/pcb-website.png END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250327T110000 DTEND;TZID=America/Toronto:20250327T113000 DTSTAMP:20260406T114601 CREATED:20250319T145412Z LAST-MODIFIED:20250319T150510Z UID:72963-1743073200-1743075000@www.cadmicro.com SUMMARY:UltiMaker S8 Speed Showdown DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/ultimaker-s8-speed-showdown/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/LP-S8Webinar-Website.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250402T090000 DTEND;TZID=America/Toronto:20250402T160000 DTSTAMP:20260406T114601 CREATED:20240129T190500Z LAST-MODIFIED:20250306T164220Z UID:55689-1743584400-1743609600@www.cadmicro.com SUMMARY:DEX Expo - Langley DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/dex-expo-langley-2/ LOCATION:Langley Events Centre\, 7888 200 Street\, Langley\, British Columbia\, V2Y 3J4\, Canada CATEGORIES:Trade Show ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/DEX-Show-Website-banner-Image.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250402T120000 DTEND;TZID=America/Toronto:20250402T160000 DTSTAMP:20260406T114601 CREATED:20240129T140148Z LAST-MODIFIED:20250226T204713Z UID:55528-1743595200-1743609600@www.cadmicro.com SUMMARY:Advanced Manufacturing Open House DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/advanced-manufacturing-open-house/ LOCATION:CAD Micro\, 30 International Blvd\, Unit 1\, Toronto\, Ontario\, M9W 1A2\, Canada CATEGORIES:In Person Event ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/SmartMTX-Event-Page-Image-1.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250407T090000 DTEND;TZID=America/Toronto:20250411T120000 DTSTAMP:20260406T114601 CREATED:20240207T152423Z LAST-MODIFIED:20250314T172251Z UID:56191-1744016400-1744372800@www.cadmicro.com SUMMARY:SOLIDWORKS PDM Administrator – Online DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-pdm-administrator/ CATEGORIES:Training ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/PDM-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250407T090000 DTEND;TZID=America/Toronto:20250411T170000 DTSTAMP:20260406T114601 CREATED:20240424T202901Z LAST-MODIFIED:20250319T183035Z UID:60811-1744016400-1744390800@www.cadmicro.com SUMMARY:SOLIDWORKS Parts\, Assemblies & Drawings – Cambridge DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-parts-assemblies-drawings-cambridge-4/ CATEGORIES:Training ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/SW-CAD-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250408T100000 DTEND;TZID=America/Toronto:20250408T110000 DTSTAMP:20260406T114601 CREATED:20240925T145920Z LAST-MODIFIED:20250314T144403Z UID:66416-1744106400-1744110000@www.cadmicro.com SUMMARY:Introduction to Using DriveWorks for Automating Your SOLIDWORKS Designs DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/introduction-to-using-driveworks-for-automating-your-solidworks-designs/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/DriveWorks-Automate-SW-Designs-Website.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250408T110000 DTEND;TZID=America/Toronto:20250408T120000 DTSTAMP:20260406T114601 CREATED:20250326T150349Z LAST-MODIFIED:20250326T151154Z UID:73103-1744110000-1744113600@www.cadmicro.com SUMMARY:Preview webinar: ZEISS ScanPort DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/preview-webinar-zeiss-scanport/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/webp:https://www.cadmicro.com/wp-content/uploads/zeiss-scanport.webp END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250410T090000 DTEND;TZID=America/Toronto:20250410T120000 DTSTAMP:20260406T114601 CREATED:20240305T165403Z LAST-MODIFIED:20250226T205528Z UID:58073-1744275600-1744286400@www.cadmicro.com SUMMARY:Simulation Hands-On Test Drive DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/simulation-hands-on-test-drive-4/ LOCATION:CAD Micro\, 30 International Blvd\, Unit 1\, Toronto\, Ontario\, M9W 1A2\, Canada CATEGORIES:In Person Event ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/Sim-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250410T110000 DTEND;TZID=America/Toronto:20250410T120000 DTSTAMP:20260406T114601 CREATED:20250407T144205Z LAST-MODIFIED:20250407T170737Z UID:73404-1744282800-1744286400@www.cadmicro.com SUMMARY:SOLIDWORKS CAM and CAMWorks - Getting Started Level 1 DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-cam-and-camworks-getting-started-level-1/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/99607285_l-1.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250414T090000 DTEND;TZID=America/Toronto:20250417T170000 DTSTAMP:20260406T114601 CREATED:20250314T145714Z LAST-MODIFIED:20250314T172016Z UID:72808-1744621200-1744909200@www.cadmicro.com SUMMARY:DriveWorks Pro Administrator - Online DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/driveworks-pro-administrator/ CATEGORIES:Training ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/Training-Banner-Image-1-1.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250414T130000 DTEND;TZID=America/Toronto:20250418T160000 DTSTAMP:20260406T114601 CREATED:20250314T144854Z LAST-MODIFIED:20250314T171845Z UID:72802-1744635600-1744992000@www.cadmicro.com SUMMARY:SOLIDWORKS Composer Essentials DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-composer-essentials/ CATEGORIES:Training ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/SW-CAD-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250415T100000 DTEND;TZID=America/Toronto:20250415T110000 DTSTAMP:20260406T114601 CREATED:20240925T172053Z LAST-MODIFIED:20250314T171413Z UID:66433-1744711200-1744714800@www.cadmicro.com SUMMARY:Introduction to Using DriveWorks as a 3D Sales Configurator DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/introduction-to-using-driveworks-as-a-3d-sales-configurator/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/DriveWorks-3D-Sales-Configurator-Website.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250415T130000 DTEND;TZID=America/Toronto:20250416T160000 DTSTAMP:20260406T114601 CREATED:20250314T151520Z LAST-MODIFIED:20250314T171530Z UID:72815-1744722000-1744819200@www.cadmicro.com SUMMARY:SOLIDWORKS PDM IT Administrator - Online DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-pdm-it-administrator-online/ CATEGORIES:Training ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/PDM-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250416T110000 DTEND;TZID=America/Toronto:20250416T120000 DTSTAMP:20260406T114601 CREATED:20250324T224428Z LAST-MODIFIED:20250409T202758Z UID:73073-1744801200-1744804800@www.cadmicro.com SUMMARY:High-Speed Layout in OrCAD X - It’s Simpler Than You Think! DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/high-speed-layout-in-orcad-x-its-simpler-than-you-think/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/Cadence-PCB-webinar-1-scaled.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250416T120000 DTEND;TZID=America/Toronto:20250416T160000 DTSTAMP:20260406T114601 CREATED:20240129T140939Z LAST-MODIFIED:20250226T204748Z UID:55538-1744804800-1744819200@www.cadmicro.com SUMMARY:Additive Manufacturing Open House DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/additive-manufacturing-open-house/ LOCATION:CAD Micro\, 30 International Blvd\, Unit 1\, Toronto\, Ontario\, M9W 1A2\, Canada CATEGORIES:In Person Event ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/3DP-1.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT END:VCALENDAR