BEGIN:VCALENDAR VERSION:2.0 PRODID:-//CAD MicroSolutions Inc. - ECPv6.15.15//NONSGML v1.0//EN CALSCALE:GREGORIAN METHOD:PUBLISH X-WR-CALNAME:CAD MicroSolutions Inc. X-ORIGINAL-URL:https://www.cadmicro.com X-WR-CALDESC:Events for CAD MicroSolutions Inc. REFRESH-INTERVAL;VALUE=DURATION:PT1H X-Robots-Tag:noindex X-PUBLISHED-TTL:PT1H BEGIN:VTIMEZONE TZID:America/Toronto BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20240310T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20241103T060000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20250309T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20251102T060000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20260308T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20261101T060000 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250402T090000 DTEND;TZID=America/Toronto:20250402T160000 DTSTAMP:20260421T224954 CREATED:20240129T190500Z LAST-MODIFIED:20250306T164220Z UID:55689-1743584400-1743609600@www.cadmicro.com SUMMARY:DEX Expo - Langley DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/dex-expo-langley-2/ LOCATION:Langley Events Centre\, 7888 200 Street\, Langley\, British Columbia\, V2Y 3J4\, Canada CATEGORIES:Trade Show ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/DEX-Show-Website-banner-Image.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250402T120000 DTEND;TZID=America/Toronto:20250402T160000 DTSTAMP:20260421T224954 CREATED:20240129T140148Z LAST-MODIFIED:20250226T204713Z UID:55528-1743595200-1743609600@www.cadmicro.com SUMMARY:Advanced Manufacturing Open House DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/advanced-manufacturing-open-house/ LOCATION:CAD Micro\, 30 International Blvd\, Unit 1\, Toronto\, Ontario\, M9W 1A2\, Canada CATEGORIES:In Person Event ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/SmartMTX-Event-Page-Image-1.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250407T090000 DTEND;TZID=America/Toronto:20250411T120000 DTSTAMP:20260421T224954 CREATED:20240207T152423Z LAST-MODIFIED:20250314T172251Z UID:56191-1744016400-1744372800@www.cadmicro.com SUMMARY:SOLIDWORKS PDM Administrator – Online DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-pdm-administrator/ CATEGORIES:Training ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/PDM-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250407T090000 DTEND;TZID=America/Toronto:20250411T170000 DTSTAMP:20260421T224954 CREATED:20240424T202901Z LAST-MODIFIED:20250319T183035Z UID:60811-1744016400-1744390800@www.cadmicro.com SUMMARY:SOLIDWORKS Parts\, Assemblies & Drawings – Cambridge DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-parts-assemblies-drawings-cambridge-4/ CATEGORIES:Training ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/SW-CAD-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250408T100000 DTEND;TZID=America/Toronto:20250408T110000 DTSTAMP:20260421T224954 CREATED:20240925T145920Z LAST-MODIFIED:20250314T144403Z UID:66416-1744106400-1744110000@www.cadmicro.com SUMMARY:Introduction to Using DriveWorks for Automating Your SOLIDWORKS Designs DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/introduction-to-using-driveworks-for-automating-your-solidworks-designs/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/DriveWorks-Automate-SW-Designs-Website.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250408T110000 DTEND;TZID=America/Toronto:20250408T120000 DTSTAMP:20260421T224954 CREATED:20250326T150349Z LAST-MODIFIED:20250326T151154Z UID:73103-1744110000-1744113600@www.cadmicro.com SUMMARY:Preview webinar: ZEISS ScanPort DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/preview-webinar-zeiss-scanport/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/webp:https://www.cadmicro.com/wp-content/uploads/zeiss-scanport.webp END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250410T090000 DTEND;TZID=America/Toronto:20250410T120000 DTSTAMP:20260421T224954 CREATED:20240305T165403Z LAST-MODIFIED:20250226T205528Z UID:58073-1744275600-1744286400@www.cadmicro.com SUMMARY:Simulation Hands-On Test Drive DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/simulation-hands-on-test-drive-4/ LOCATION:CAD Micro\, 30 International Blvd\, Unit 1\, Toronto\, Ontario\, M9W 1A2\, Canada CATEGORIES:In Person Event ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/Sim-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250410T110000 DTEND;TZID=America/Toronto:20250410T120000 DTSTAMP:20260421T224954 CREATED:20250407T144205Z LAST-MODIFIED:20250407T170737Z UID:73404-1744282800-1744286400@www.cadmicro.com SUMMARY:SOLIDWORKS CAM and CAMWorks - Getting Started Level 1 DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-cam-and-camworks-getting-started-level-1/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/99607285_l-1.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250414T090000 DTEND;TZID=America/Toronto:20250417T170000 DTSTAMP:20260421T224954 CREATED:20250314T145714Z LAST-MODIFIED:20250314T172016Z UID:72808-1744621200-1744909200@www.cadmicro.com SUMMARY:DriveWorks Pro Administrator - Online DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/driveworks-pro-administrator/ CATEGORIES:Training ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/Training-Banner-Image-1-1.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250414T130000 DTEND;TZID=America/Toronto:20250418T160000 DTSTAMP:20260421T224954 CREATED:20250314T144854Z LAST-MODIFIED:20250314T171845Z UID:72802-1744635600-1744992000@www.cadmicro.com SUMMARY:SOLIDWORKS Composer Essentials DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-composer-essentials/ CATEGORIES:Training ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/SW-CAD-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250415T100000 DTEND;TZID=America/Toronto:20250415T110000 DTSTAMP:20260421T224954 CREATED:20240925T172053Z LAST-MODIFIED:20250314T171413Z UID:66433-1744711200-1744714800@www.cadmicro.com SUMMARY:Introduction to Using DriveWorks as a 3D Sales Configurator DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/introduction-to-using-driveworks-as-a-3d-sales-configurator/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/DriveWorks-3D-Sales-Configurator-Website.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250415T130000 DTEND;TZID=America/Toronto:20250416T160000 DTSTAMP:20260421T224954 CREATED:20250314T151520Z LAST-MODIFIED:20250314T171530Z UID:72815-1744722000-1744819200@www.cadmicro.com SUMMARY:SOLIDWORKS PDM IT Administrator - Online DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-pdm-it-administrator-online/ CATEGORIES:Training ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/PDM-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250416T110000 DTEND;TZID=America/Toronto:20250416T120000 DTSTAMP:20260421T224954 CREATED:20250324T224428Z LAST-MODIFIED:20250409T202758Z UID:73073-1744801200-1744804800@www.cadmicro.com SUMMARY:High-Speed Layout in OrCAD X - It’s Simpler Than You Think! DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/high-speed-layout-in-orcad-x-its-simpler-than-you-think/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/Cadence-PCB-webinar-1-scaled.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250416T120000 DTEND;TZID=America/Toronto:20250416T160000 DTSTAMP:20260421T224954 CREATED:20240129T140939Z LAST-MODIFIED:20250226T204748Z UID:55538-1744804800-1744819200@www.cadmicro.com SUMMARY:Additive Manufacturing Open House DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/additive-manufacturing-open-house/ LOCATION:CAD Micro\, 30 International Blvd\, Unit 1\, Toronto\, Ontario\, M9W 1A2\, Canada CATEGORIES:In Person Event ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/3DP-1.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250416T140000 DTEND;TZID=America/Toronto:20250416T143000 DTSTAMP:20260421T224954 CREATED:20250313T181538Z LAST-MODIFIED:20250314T155834Z UID:72675-1744812000-1744813800@www.cadmicro.com SUMMARY:The Ultimate PCB Design Upgrade: Why Engineers Choose OrCAD X DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/the-ultimate-pcb-design-upgrade-why-engineers-choose-orcad-x/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/orcad_x_solo-1.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250417T100000 DTEND;TZID=America/Toronto:20250417T160000 DTSTAMP:20260421T224954 CREATED:20240305T181712Z LAST-MODIFIED:20250226T205604Z UID:58121-1744884000-1744905600@www.cadmicro.com SUMMARY:Simulation Demo Day DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/simulation-demo-day-4/ LOCATION:CAD Micro\, 30 International Blvd\, Unit 1\, Toronto\, Ontario\, M9W 1A2\, Canada CATEGORIES:In Person Event ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/Adv-Sim-Summit-Website-Image.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250417T110000 DTEND;TZID=America/Toronto:20250417T120000 DTSTAMP:20260421T224954 CREATED:20250407T152709Z LAST-MODIFIED:20250407T170654Z UID:73414-1744887600-1744891200@www.cadmicro.com SUMMARY:SOLIDWORKS CAM and CAMWorks - Getting Started with the TechDB DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-cam-and-camworks-getting-started-with-the-techdb/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/Man-at-Computer-w-CAMWorks-New-Logo.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250417T140000 DTEND;TZID=America/Toronto:20250417T143000 DTSTAMP:20260421T224954 CREATED:20250407T181417Z LAST-MODIFIED:20250407T185242Z UID:73467-1744898400-1744900200@www.cadmicro.com SUMMARY:5 Benefits of All-in-One CAD/CAM for a Wide Range of Machines - with Modern Machine Shop DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/5-benefits-of-all-in-one-cad-cam-for-a-wide-range-of-machines/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/CAMWorks-3-Axis-Milling2-1.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250421T090000 DTEND;TZID=America/Toronto:20250423T120000 DTSTAMP:20260421T224954 CREATED:20240424T195908Z LAST-MODIFIED:20250313T201711Z UID:60773-1745226000-1745409600@www.cadmicro.com SUMMARY:SOLIDWORKS Simulation Premium: Dynamics – Online DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-simulation-premium-dynamics-online/ CATEGORIES:Training ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/Sim-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250421T090000 DTEND;TZID=America/Toronto:20250501T120000 DTSTAMP:20260421T224954 CREATED:20250313T151404Z LAST-MODIFIED:20250313T151521Z UID:72621-1745226000-1746100800@www.cadmicro.com SUMMARY:SOLIDWORKS Essentials - Online DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-essentials-online-3/ CATEGORIES:Training ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/SW-CAD-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250421T130000 DTEND;TZID=America/Toronto:20250422T160000 DTSTAMP:20260421T224954 CREATED:20241126T163336Z LAST-MODIFIED:20250313T200744Z UID:68743-1745240400-1745337600@www.cadmicro.com SUMMARY:SOLIDWORKS Electrical 3D - Online DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-electrical-3d-online/ CATEGORIES:Training ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/Electrical-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250421T130000 DTEND;TZID=America/Toronto:20250422T160000 DTSTAMP:20260421T224954 CREATED:20250313T203851Z LAST-MODIFIED:20250314T171330Z UID:72754-1745240400-1745337600@www.cadmicro.com SUMMARY:SOLIDWORKS File Management - Online DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-file-management-online/ CATEGORIES:Training ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/SW-CAD-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250421T130000 DTEND;TZID=America/Toronto:20250424T160000 DTSTAMP:20260421T224954 CREATED:20250314T152823Z LAST-MODIFIED:20250314T171205Z UID:72821-1745240400-1745510400@www.cadmicro.com SUMMARY:SOLIDWORKS Motion - Online DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-motion-online/ CATEGORIES:Training ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/Sim-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250421T130000 DTEND;TZID=America/Toronto:20250425T160000 DTSTAMP:20260421T224954 CREATED:20240424T203123Z LAST-MODIFIED:20250314T172332Z UID:60818-1745240400-1745596800@www.cadmicro.com SUMMARY:SOLIDWORKS PDM Administrator – Online DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-pdm-administrator-2/ CATEGORIES:Training ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/PDM-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250422T100000 DTEND;TZID=America/Toronto:20250422T110000 DTSTAMP:20260421T224954 CREATED:20240926T145652Z LAST-MODIFIED:20250314T144559Z UID:66530-1745316000-1745319600@www.cadmicro.com SUMMARY:Introduction to Creating a CPQ Solution Using DriveWorks DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/introduction-to-creating-a-cpq-solution-using-driveworks-2/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/DriveWorks-3D-Sales-Configurator-Website.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250422T130000 DTEND;TZID=America/Toronto:20250501T160000 DTSTAMP:20260421T224954 CREATED:20240814T162323Z LAST-MODIFIED:20250313T193839Z UID:65310-1745326800-1746115200@www.cadmicro.com SUMMARY:CAMWorks 3 Axis Milling – Online DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/camworks-3-axis-online/ CATEGORIES:Training ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/CAM-Training-Thumbnail.jpg ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250423T090000 DTEND;TZID=America/Toronto:20250423T110000 DTSTAMP:20260421T224954 CREATED:20250306T164628Z LAST-MODIFIED:20250414T142438Z UID:72341-1745398800-1745406000@www.cadmicro.com SUMMARY:Precision 3D Scanning for Medical Devices: Live Demo of ZEISS ATOS Q DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/precision-3d-scanning-for-medical-devices-live-demo-of-zeiss-atos-q/ LOCATION:CAD Micro\, 30 International Blvd\, Unit 1\, Toronto\, Ontario\, M9W 1A2\, Canada CATEGORIES:In Person Event ATTACH;FMTTYPE=image/webp:https://www.cadmicro.com/wp-content/uploads/WebinarEvent-Template-4.webp ORGANIZER;CN="CAD Micro":MAILTO:contact@cadmicro.com END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250423T150000 DTEND;TZID=America/Toronto:20250423T160000 DTSTAMP:20260421T224954 CREATED:20250410T195404Z LAST-MODIFIED:20250410T195646Z UID:73548-1745420400-1745424000@www.cadmicro.com SUMMARY:Introducing the Artec Point: A New Player in 3D inspection DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/introducing-the-artec-point-a-new-player-in-3d-inspection/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/event_b835e146-f214-4ef4-989e-69af4f7074f6_resources_EnlSr0idQo6rTNuB40UO_post-process-tools-and-techniques.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250424T110000 DTEND;TZID=America/Toronto:20250424T120000 DTSTAMP:20260421T224954 CREATED:20250407T170850Z LAST-MODIFIED:20250407T171207Z UID:73460-1745492400-1745496000@www.cadmicro.com SUMMARY:SOLIDWORKS CAM and CAMWorks - Getting Started Level 2 DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-cam-and-camworks-getting-started-level-2-3/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/Man-at-computer.jpg END:VEVENT BEGIN:VEVENT DTSTART;TZID=America/Toronto:20250424T150000 DTEND;TZID=America/Toronto:20250424T160000 DTSTAMP:20260421T224954 CREATED:20250410T195748Z LAST-MODIFIED:20250410T200033Z UID:73556-1745506800-1745510400@www.cadmicro.com SUMMARY:SOLIDWORKS Thermal Stress from Beginning to End DESCRIPTION:Live \n \n \n \n \n \n \n \n Webinar \n \n \n \n \n \n \n \n March 26 @ 11am ET \n \n \n \n \n \n \n \n \n \n \n \n Leveraging Constraint Sets for DDRx Design in Allegro X \n \n \n \n \n \n \n \n \n \n \n \n Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times\, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach\, PCB designers can rapidly route and verify complex bus structures.  Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints  Save your spot now\, we hope to see you there. \n \n \n \n \n \n \n Register Now URL:https://www.cadmicro.com/event/solidworks-thermal-stress-from-beginning-to-end/ CATEGORIES:Webinar ATTACH;FMTTYPE=image/jpeg:https://www.cadmicro.com/wp-content/uploads/event_4bca768e-c667-4c24-9b90-d211c82c861b_resources_tk7gJl8YSNKQGJ7LbyHf_solidworks-thermal-stress-from-begining-to-end.jpg END:VEVENT END:VCALENDAR