CAD MicroSolutions Inc.

Simulation Demo Day
2025-03-20 09:00 - 16:00, 2025-04-17 10:00 - 16:00 (America/Toronto) | CAD Micro, 30 International Blvd, Unit 1, Toronto, Ontario, M9W 1A2, Canada
Live

Webinar

March 26 @ 11am ET

Leveraging Constraint Sets for DDRx Design in Allegro X

Today’s PCB designers must create increasingly complex boards and systems. With tighter design densities and a demand for faster turnaround times, they must quickly route critical signals while staying within electrical and physical constraints. Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals. Utilizing a constraint-driven design approach, PCB designers can rapidly route and verify complex bus structures. Join a webinar by Cadence and learn about: Define impedance requirements through the Cross Section EditorUse Constraint Sets (CSets) to apply rules to bus structures -e.g. DDRx buses quickly Leverage Timing vision to route signalsUse Auto-interactive delay tuning to verify compliance with constraints Save your spot now, we hope to see you there.

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