BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//CAD MicroSolutions Inc. - ECPv6.15.15//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-WR-CALNAME:CAD MicroSolutions Inc.
X-ORIGINAL-URL:https://www.cadmicro.com
X-WR-CALDESC:Events for CAD MicroSolutions Inc.
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:America/Toronto
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20240310T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20241103T060000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20250309T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20251102T060000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20260308T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20261101T060000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=America/Toronto:20250430T110000
DTEND;TZID=America/Toronto:20250430T113000
DTSTAMP:20260405T161326
CREATED:20250422T193643Z
LAST-MODIFIED:20250422T194846Z
UID:73735-1746010800-1746012600@www.cadmicro.com
SUMMARY:Accelerating System Design with Integrated Analysis in Allegro X
DESCRIPTION:Live				\n				\n					\n		\n				\n			\n						\n				\n					Webinar				\n				\n					\n		\n					\n		\n				\n				\n					April 30 @ 11am ET				\n				\n				\n				\n							\n			\n						\n		\n						\n				\n				\n				\n					Accelerating System Design with Integrated Analysis in Allegro X				\n				\n					\n		\n					\n		\n				\n						\n					\n			\n						\n				\n									With the EE Cockpit in Allegro X\, electrical engineers (EEs) can run analyses during the schematic design phase without complicated analysis setups or specialized models to obtain meaningful results. With in-design analysis\, EEs can provide accurate constraints to the PCB designer and verify that these constraints are met after the design is routed. Additionally\, EEs can perform PI and thermal analysis to ensure a high-quality PDN design. Join a webinar by Cadence and explore the following topics to be covered during the webinar: Topology exploration to do pre-route “what if” analysis and drive meaningful constraints to the PCB layout designerPower integrity analysis with easy setup of the design’s power topologyThermal analysis integration to ensure that board-level thermal constraints are met  Save your spot now\, we hope to see you there!   								\n				\n				\n				\n									\n					\n						\n									Register Now
URL:https://www.cadmicro.com/event/accelerating-system-design-with-integrated-analysis-in-allegro-x/
CATEGORIES:Webinar
ATTACH;FMTTYPE=image/png:https://www.cadmicro.com/wp-content/uploads/pcb-website.png
END:VEVENT
END:VCALENDAR